Home Technique • Analog Circuit Design: Fractional-N Synthesizers, Design for by Arthur H.M. van Roermund, Michiel Steyaert, Johan Huijsing

Analog Circuit Design: Fractional-N Synthesizers, Design for by Arthur H.M. van Roermund, Michiel Steyaert, Johan Huijsing

By Arthur H.M. van Roermund, Michiel Steyaert, Johan Huijsing

This ebook comprises the contribution of 18 tutorials of the twelfth Workshop on Advances in Analog Circuit layout. it truly is quantity 12 within the winning sequence of Analog Circuit layout, offering invaluable info and perfect overviews of analog circuit layout, CAD, and RF platforms. The sequence may be visible as a connection with these excited about analog and mixed-signal layout. every one ebook discusses 3 particular themes on new and important layout principles within the quarter of analog circuit layout. every one subject is mentioned by means of six specialists within the box and cutting-edge info is shared and overviewed. during this twelfth variation the themes are Fractional-N Synthesizers, layout for Robustness, and Line and Bus Drivers. Analog Circuit layout is a vital reference resource for analog layout engineers and researchers that desire to preserve abreast with the newest advancements within the box. the educational assurance additionally makes it compatible to be used in a sophisticated layout direction.

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Extra resources for Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers

Example text

In practice, any practical system also includes parasitic poles and zeros that have second order effects on G(f). Discussion of the impact of such parasitics is deferred to the design manual that comes with the PLL Design Assistant program. 2. Type The type of a PLL is defined as the number of integrators in its open loop transfer function. In practical PLL implementations, the type is either I or II (note that the VCO contributes one integrator, so the type must be at least I). A type I PLL does not contain an integrator in its loop filter transfer function, whereas a type II PLL does contain an integrator in its loop filter transfer function.

This is reflected in the large effort put in monolithic CMOS integration of RF circuits both by academics and industry [1–3]. The goal of this work is the monolithic integration in standard CMOS technology of a frequency synthesizer to enable the full integration of a transceiver front- 51 A. van Roermund et al. ), Analog Circuit Design, 51-75. © 2003 Kluwer Academic Publishers. Printed in the Netherlands. 52 end in CMOS [1]. The fractional-N synthesizer topology presents an elegant solution [4]; It circumvents the severe speed-spectral purity-resolution trade-off of the classic PLL synthesizer by providing synthesis of fractional multiples of the reference frequency.

Reinhardt, “Spur reduction techniques in direct digital synthesizers,” in Proceedings of 47th Frequency Control Symposium, Oct. 1993, pp. 230241. W. Rhee and A. Ali, “An on-chip phase-compensation technique in fractional-N frequency synthesis,” in IEEE Proceedings of ISCAS, vol. 3, May 1999, pp. 363-366. T. A. Riley, M. Copeland, and T. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, pp. 553-559, May 1993. B. Miller and R.

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